There are various types of one-time programmable memory (OTPM) arrays that represent embedded non-volatile memory (NVM) technologies. In a specific type of OTPM, a write operation occurs over many write-verify cycles to achieve a large threshold voltage shift of a memory twin-cell. Further, depending on mismatches within an OTPM twin-cell, the number of write-verify cycles may vary significantly. Each of the write operations include a write followed by a bitline leakage test to check for dielectric breakdown and also a verify (i.e., read) to check if the cell is written.
In OTPM systems, the operations of the memory are performed one address at a time. For example, a single write operation may take approximately 8 milliseconds. Further, programming occurs with a high wordline voltage (approximately 2 volts) and a high (i.e., elevated) source line (approximately 1.5 volts) which induces an approximate 2 mA current flowing through the transistor being programmed. This high stress operation forces electrons to be trapped in the oxide of the transistor being programmed, shifting the threshold voltage of the transistor. This type of OTPM is referred to as a charge trap memory. In this scenario, a time dependent dielectric breakdown (TDDB) results in a wordline to bitline short with a resistance, which causes other parallel cells to have a crippled wordline during programming and reading.